TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 31

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.4.1
General Interrupt Servicing
operations are the same as those performed by the TLCS-900/L and TLCS-900/H.
(1) Reads an interrupt vector from the interrupt controller.
(2) Pushes the contents of the program counter (PC) and status register (SR) to the stack
(3) Sets the interrupt mask register bits <IFF2:0> to one level higher than the accepted
(4) Increments the interrupt nesting counter INTNEST by one.
(5) Makes a branch to the address specified with the data stored at address “FFFF00H +
the main routine. The RETI instruction restores the contents of the PC and SR from the
stack and decrements the INTNEST by one.
are disabled.
Table 3.4.1 shows the interrupt vector table.
request is sampled immediately after the first instruction of the current interrupt service
routine is executed. The DI instruction can be used as the first instruction in an interrupt
service routine to prohibit nesting of maskable interrupts.
data bus and 0-wait cycles).
be disabled or enabled programmatically and a priority level can be specified for each
interrupt source. The CPU accepts an interrupt if its priority level is higher than or equal
to the value stored in the CPU’s <IFF2:0> bits. The CPU then sets the <IFF2:0> bits to the
accepted priority level plus one. This enables the CPU to accept any higher-priority
interrupt that occurs while servicing the current interrupt, so that interrupts are nested.
The CPU performs the following operations once it accepts an interrupt. These
The above procedure requires 18 states (1.33 µs at 27 MHz) in the best case (with 16-bit
Upon completion of interrupt servicing, the RETI instruction is usually used to return to
Nonmaskable interrupts cannot be disabled programmatically. Maskable interrupts can
If another interrupt request is issued while the CPU is performing the above steps, the
Upon a system reset, the <IFF2:0> bits are initialized to 7 so that maskable interrupts
Addresses FFFF00H to FFFFFFH (256 bytes) are assigned to the interrupt vector area.
If two or more interrupts having the same priority level occur simultaneously, the
interrupt controller generates an interrupt vector according to default priorities (fixed,
higher priorities assigned to smaller vector values) and clears the interrupt request.
area indicated by the XSP.
interrupt level. If the level is 7, however, the CPU sets <IFF2:0> to 7 without
incrementing the value.
interrupt vector” and then starts the interrupt service routine.
91CW40-29
TMP91CW40
2008-09-19