TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 185
TMP91xy40FG
Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP91XY40FG.pdf
(213 pages)
Specifications of TMP91xy40FG
Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
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ADREG26L
ADREG37L
ADREG37H
ADREG26H
(02A4H)
(02A6H)
(02A7H)
(02A5H)
Channel x conversion
result bits
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Lower 2 bits of an AD
Lower 2 bits of an AD
ADR21
ADR29
ADR31
ADR39
conversion result
conversion result
7
7
7
7
Undefined
Undefined
R
R
ADREGxH
Figure 3.16.5 AD Conversion Registers (4)
9
ADR20
ADR28
ADR30
ADR38
7
6
6
6
6
AD Conversion Result High Register 3/7
AD Conversion Result High Register 2/6
8
AD Conversion Result Low Register 2/6
AD Conversion Result Low Register 3/7
6
7
5
ADR27
ADR37
4
5
5
Upper 8 bits of an AD conversion result
5
5
Upper 8 bits of an AD conversion result
6
91CW40-183
3
5
2
ADR26
ADR36
4
•
•
4
4
4
4
1
Undefined
Undefined
Bits 5 to 1 are always read as 1.
Bit0 (<ADRxRF>), when set, indicates that the conversion
result has been stored in the ADREGxH/L register pair.
This bit is cleared when either the ADREGxH or
ADREGxL is read.
3
0
R
R
2
ADR25
ADR35
3
3
3
3
1
7
0
6
ADR24
ADR34
5
2
2
2
2
4
3
ADR23
ADR33
2
1
1
1
1
ADREGxL
1
0
Conversion
result store
flag
1: Stored
Conversion
result store
flag
1: Stored
TMP91CW40
ADR2RF
ADR3RF
ADR22
ADR32
2008-09-19
0
R
0
0
R
0
0
0
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