TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 23

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(2) Wakeup signaling
Availability of wakeup signaling depends on the settings of the interrupt mask level
bits, <IFF2:0>, of the CPU status register (SR) and the current HALT mode (see Table
3.3.4).
• Wakeup via interrupt signaling
• Wakeup via reset signaling
There are two ways to exit a HALT mode: An interrupt request or reset signal.
interrupt priority level programmed before executing the HALT instruction. If the
interrupt priority level is greater than or equal to the processor’s interrupt mask
level, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the HALT instruction. If the interrupt priority level is less
than the processor’s interrupt mask level, the HALT mode is not terminated.
(Nonmaskable interrupts are always serviced upon return from a HALT mode,
regardless of the current interrupt mask level.)
interrupts can, however, terminate a HALT mode even if the interrupt priority
level is less than the processor’s interrupt mask level. In that case, program
execution resumes with the instruction immediately following the HALT
instruction without executing the interrupt service routine. (The interrupt request
flag remains set.)
wakeup from STOP mode must allow sufficient time for the oscillator to restart
and stabilize (see Table 3.3.5).
everything else, whereas an interrupt preserves all internal states that were in
effect before the HALT mode was entered.
The operation upon return from a HALT mode varies, depending on the
Only INT0, INT1, KWI0 to KWI3, INTRTC and INTALM0 to INTALM4
Reset signaling always brings the TMP91CW40 out of any HALT mode. A
A reset does not affect the contents of the internal RAM, but initializes
91CW40-21
TMP91CW40
2008-09-19