MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 24

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
REGISTER 3-1:
3.6
The PIC12F683 includes a feature that allows the
system clock source to be switched between the main
oscillator and the internal clock source.
Essentially, there are two clock sources for this device:
• Primary oscillators
• Secondary oscillator (i.e., internal oscillator block
The Primary Oscillators include the external Crystal
and Resonator modes, the external RC modes, the
External Clock mode and the internal oscillator block.
The mode is defined on POR by the contents of
configuration word. The clock sources for the
PIC12F683 are shown in Figure 3-6. See Section 12.0
“Special Features of the CPU” for configuration word
details.
The Secondary Oscillator is the internal oscillator
block which is comprised of two independent internal
oscillators; an uncalibrated 31 kHz INTRC and a
calibrated 8 MHz INTOSC with a dedicated postscaler.
DS41211A-page 22
INTOSC and INTRC)
Note:
Clock Sources and Oscillator
Switching
bit 7-5
bit 4-0
The PIC12F683 uses a factory calibrated
8 MHz internal oscillator (INTOSC) and
postscaler to provide the 125 kHz to
8 MHz system clock frequencies.
OSCTUNE — OSCILLATOR TUNING REGISTER (ADDRESS 90h)
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Center frequency. Oscillator Module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
bit 7
Legend:
R = Readable bit
-n = Value at POR
U-0
—
U-0
—
Advance Information
U-0
—
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN4
3.6.1
The OSCCON register (Register 3-2) controls several
aspects of the system clock’s operation.
The System Clock Select bit, SCS (OSCCON<0>),
selects the clock source that is used. When the bit is
cleared, the system clock source comes from the
primary oscillator selected by the FOSC2:FOSC0 bits
in configuration word. When the bit is set, the system
clock source is provided by the internal oscillator block.
After a Reset, SCS is always cleared. Any automatic
clock switch which may occur from Two-speed Start-up
or Fail-Safe Clock Monitor does not update the SCS bit.
The user can monitor the OSTS (OSCCON<3>) to
determine the current system clock source.
The internal oscillator select bits IRCF2:IRCF0
(OSCCON<6:4>) select the frequency output of the
internal oscillator block that is used to drive the system
clock. The choices are the INTRC source (31 kHz), the
INTOSC source (8 MHz), or one of the six frequencies
derived from the INTOSC postscaler (125 kHz to
4 MHz).
The
(OSCCON<1>) bits indicate the status of the primary
oscillator, 8 MHz INTOSC and 31 kHz INTRC; these
bits are set when their respective oscillators are stable.
In particular, OSTS indicates that the Oscillator Start-up
Timer has timed out.
Note:
OSTS,
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
OSCCON REGISTER
Following any Reset, the IRCF bits are set
to ‘110’ and the frequency selection is
forced to 4 MHz. The user can modify the
IRCF bits to select a different frequency.
HTS
R/W-0
TUN2
 2003 Microchip Technology Inc.
(OSCCON<2>)
x = Bit is unknown
R/W-0
TUN1
and
R/W-0
TUN0
bit 0
LTS