MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 89

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.4
The PIC12F683 has 10 sources of interrupt:
• External Interrupt GP2/INT
• TMR0 Overflow Interrupt
• GPIO Change Interrupts
• Comparator Interrupt
• A/D Interrupt
• Timer 1 Overflow Interrupt
• Timer 2 Match Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
The Interrupt Control register (INTCON) and Periph-
eral Interrupt register (PIR1) record individual interrupt
requests in flag bits. The INTCON register also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register and PIE1 register. GIE is cleared on
Reset.
The return from interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• GPIO Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in Special Register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM data write interrupt
• A/D Interrupt
• Comparator Interrupt
• Timer1 Overflow Interrupt
• Timer 2-match Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
 2003 Microchip Technology Inc.
Interrupts
Advance Information
For external interrupt events, such as the INT pin or
GPIO change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer 1, Timer 2,
Comparator, A/D, Data EEPROM, CCP modules, refer
to
Section 12.6.4 “Fail-Safe Clock Monitor” for more
information.
Note 1: Individual interrupt flag bits are set,
the
2: When an instruction that clears the GIE
respective
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
of
peripheral
PIC12F683
the
status
DS41211A-page 87
section.
of
their
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