MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 95

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.6.3
Two-speed Start-up minimizes the latency between
oscillator start-up and code execution that may be
selected with the IESO (Internal/External Switch Over)
bit in configuration word. This mode is achieved by
initially using the INTOSC for code execution until the
primary oscillator is stable. This results in code
execution with a minimum delay. See Section 3.5
“Internal Oscillator Block” for more information.
If this mode is enabled and any of the following
conditions exist, the system will begin execution with
the INTOSC oscillator.
• POR and after the Power-up Timer has expired (if
• or following a wake-up from Sleep,
• or a Reset when running from INTOSC. After a
If the primary oscillator is configured to be anything
other than XT, LP, or HS, then Two-speed Start-up is
disabled, because the primary oscillator will not
require any time to become stable after POR, or an
exit from Sleep.
FIGURE 12-10:
 2003 Microchip Technology Inc.
Program Counter
PWRTEN = ‘0’),
Reset, SCS bit (OSCCON<0>) is always cleared.
Note:
System Clock
INTOSC
Following any Reset, the IRCF bits are set
to ‘110’ and the frequency selection is
forced to 4 MHz. The user can modify the
IRCF bits to select a different internal oscil-
lator frequency.
TWO-SPEED CLOCK START-UP
MODE
OSC1
OSC2
Q1
TWO-SPEED START-UP
0
Q2
1
T
T
OST
Q3
1022 1023
PC
Q4
Advance Information
Q1
Q2
Checking the state of the OSTS bit will confirm
whether the primary clock configuration is engaged. If
the OSTS bit is set, the device is running from the
primary clock source as defined by the F
configuration word. If the system clock is being
generated from the INTOSC as the secondary clock
source then OSTS bit will be clear.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
12.6.3.1
1.
2.
3.
4.
5.
6.
7.
The software may read the OSTS bit to determine
when the switch over takes place so that any software
timing can be adjusted.
Note:
Wake-up from Sleep, Reset or POR.
Instructions begin execution by INTOSC at the
frequency set in the IRCF bits (OSCCON<6:4>).
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of INTOSC.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT, or HS).
System clock is switched to primary source.
PC + 1
Executing a SLEEP instruction will abort
the Oscillator Start-up Time and will cause
the OSTS bit (OSCCON<3>) to remain
clear.
Two-speed Start-up Sequence
Q3
PIC12F683
Q4
DS41211A-page 93
PC + 2
OSC
Q1
bits in the