MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 93

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.6
For PIC12F683, the WDT has been modified from
previous PIC16 devices. The new WDT is code and
functionally backward compatible with previous PIC16
WDT modules, and allows the user to have a scaler
value for the WDT and TMR0 at the same time. In
addition, the WDT time-out value can be extended to
268 seconds, using the prescaler with the postscaler
when PSA is set to ‘1’.
12.6.1
The WDT derives its time base from the 31 kHz
INTRC; therefore, the accuracy of the 31 kHz will be
the same accuracy for the WDT time-out period. The
LTS (OSCCON<1>) Status bit does not reflect that the
INTRC is enabled.
The value of WDTCON is ‘---0 1000’ on all Resets.
This gives a nominal time base of 18 ms, which is
compatible with the time base generated with previous
PIC16 microcontroller versions.
FIGURE 12-9:
TABLE 12-8:
 2003 Microchip Technology Inc.
WDTEN = ‘0’
CLRWDT command
OSC FAIL detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Note:
INTRC Clock
31 kHz
Watchdog Timer (WDT)
Note1: This is the shared Timer 0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
WDT OSCILLATOR
PRESCALER/POSTSCALER BIT STATUS
WATCHDOG TIMER BLOCK DIAGRAM
Conditions
16-bit Programmable Prescaler WDT
WDTEN from Configuration Word
SWDTEN from WDTCON
WDTPS<3:0>
Advance Information
From TMR0 Clock Source
A new prescaler has been added to the path between
the INTRC and the multiplexors used to select the path
for the WDT. This prescaler is 16 bits and can be
programmed to divide the INTRC by 128 to 65536,
giving the time base used for the WDT a nominal
range of 1 ms to 268s.
12.6.2
The WDTEN bit is located in configuration word and
when this bit is set, the WDT runs continuously.
When the WDTEN bit in the Configuration Word
register is set, the SWDTEN bit (WDTCON<0>) has
no effect. If WDTEN is clear, then the SWDTEN bit can
be used to enable and disable the WDT. Setting the bit
will enable it and clearing the bit will disable it.
The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the PIC16
family of microcontrollers. See Section 5.0 “Timer0
Module” for more information.
Cleared at end of OST
0
1
Prescaler
WDT CONTROL
Cleared
PSA
WDT Time-out
0
PIC12F683
Prescaler
Cleared at end of OST
Postscaler (PSA = 1)
1
8
(1)
DS41211A-page 91
Cleared
PSA
TO TMR0
PS<2:0>