MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 98

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
12.7
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the Status Register is cleared
• TO bit is set
• Oscillator driver is turned off
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparator and CV
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or V
tion from on-chip pull-ups on GPIO should be
considered.
The MCLR pin must be at a logic high level.
12.7.1
The device can wake-up from Sleep through one of
the following events:
1.
2.
3.
The first event will cause a device Reset. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the Status Register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT Wake-up
occurred.
The following peripheral interrupts can wake the
device from Sleep:
1.
2.
3.
4.
5.
6.
7.
8.
DS41211A-page 96
SLEEP was executed (driving high, low or
hi-impedance).
Note:
SS
External Reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from GP2/INT pin, GPIO change or a
peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
Comparator output changes state.
Interrupt-on-change.
External interrupt from INT pin.
for lowest current consumption. The contribu-
Power-Down Mode (Sleep)
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
REF
should be disabled. I/O pins
DD
or V
SS
, with no external
Advance Information
DD
instruction should be executed before a SLEEP
instruction.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-
up is regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution
at the instruction after the SLEEP instruction. If the GIE
bit is set (enabled), the device executes the instruction
after the SLEEP instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.7.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP
instruction was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
Note:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
WAKE-UP USING INTERRUPTS
 2003 Microchip Technology Inc.