MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 97

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

FIGURE 12-12:
12.6.4.2
The FSCM is designed to detect oscillator failure at
any point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired.
If the primary system clock is EC or RC mode,
monitoring will begin immediately following these
events. For HS, LP or XT mode, the situation is
somewhat different. Since the oscillator may require a
start-up time considerably longer than the FSCM
sample clock time, a false clock failure may be
detected. To prevent this, the internal oscillator block is
automatically configured as the system clock and
functions until the primary clock is stable (the OST has
timed out). This is identical to Two-speed Start-up
mode. Once the primary clock is stable, the INTRC
returns to its role as the FSCM source.
 2003 Microchip Technology Inc.
Note:
Sample Clock
Note:
CM Output
OSCFIF
System
Output
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switch-over have successfully completed.
Clock
Reset or Wake-up From Sleep
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
FSCM TIMING DIAGRAM
CM Test
Advance Information
CM Test
Oscillator
Failure
Detected
PIC12F683
Failure
CM Test
DS41211A-page 95