MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 61

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

REGISTER 9-2:
9.4
The comparator output is read through the CMCON0
register. This bit is read-only. The comparator output
may also be directly output to the GP2 pin. When
enabled, multiplexors in the output path of the GP2 pin
will switch and the output will be the unsynchronized
output of the comparator. The uncertainty of the
the response time given in the specifications.
Figure 9-4 shows the output block diagram for the
comparator.
The TRISIO bit will still function as an output
enable/disable for the GP2 pin while in this mode.
The polarity of the comparator outputs can be changed
using the CINV bit (CMCON0<4>).
Timer1 gate source can be configured to use the T1G
pin or the comparator output as selected by the T1GSS
bit (CMCON1<1>). This feature can be used to time the
duration or interval of analog events. The output of the
comparator can also be synchronized with Timer1 by
setting the CMSYNC bit (CMCON1<0>). When
enabled, the output of comparator is latched on the
falling edge of Timer1 clock source. If a prescaler is
used with Timer1, the comparator is latched after the
prescaler. To prevent a race condition, the comparator
output is latched on the falling edge of the Timer1 clock
source and Timer1 increments on the rising edge of its
clock source. See the Comparator Block Diagram
(Figure 9-4)
(Figure 6-1) for more information.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the compara-
tor is used as the Timer1 gate source. This ensures
Timer1 does not miss an increment if the comparator
changes during an increment.
 2003 Microchip Technology Inc.
comparator is related to the input offset voltage and
Comparator Output
bit 7-2:
bit 1
bit 0
and
the
CMCON1 — COMPARATOR CONFIGURATION REGISTER (ADDRESS: 1Ah)
Unimplemented: Read as ‘0’
T1GSS: Timer 1 Gate Source Select bit
1 = Timer 1 Gate Source is T1G pin (GP4 must be configured as digital input)
0 = Timer 1 Gate Source is comparator output
CMSYNC: Comparator Synchronize bit
1 = COUT Output synchronized with falling edge of Timer 1 Clock
0 = COUT Output not synchronized with Timer 1 Clock
Legend:
R = Readable bit
- n = Value at POR
bit 7
U-0
Timer1
—
Block
U-0
—
Advance Information
Diagram
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
9.5
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bit, as read from CMCON0<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a '1' to this register, a
simulated interrupt may be initiated.
The
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bits CMIF.
Reading CMCON0 will end the mismatch condition and
allow flag bits CMIF to be cleared.
Note:
Any read or write of CMCON0. This will end the
mismatch condition.
Clear flag bits CMIF.
CMIE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Comparator Interrupt
U-0
—
If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF (PIR1<3>) inter-
rupt flags may not get set.
bit
(PIE1<3>)
U-0
—
PIC12F683
x = Bit is unknown
and
T1GSS
R/W-1
DS41211A-page 59
the
CMSYNC
PEIE
R/W-0
bit 0
bit