MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 46
MCP1726T-ADJZEMF
Manufacturer Part Number
MCP1726T-ADJZEMF
Description
Regulator, Extended Industrial, HVSON, 8-Pin|
Manufacturer
Microchip Technology
Datasheet
1.MCP1726T-ADJZEMF.pdf
(154 pages)
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PIC12F683
6.1
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock or
run asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the Timer 1 gate, which can be
selected as either the T1G pin or the comparator
output.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
6.2
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
FIGURE 6-2:
DS41211A-page 44
Note:
Note:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
Timer1 Modes of Operation
Timer1 Interrupt
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
clock.
TIMER1 INCREMENTING EDGE
Advance Information
6.3
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
6.4
Timer1 gate source is software configurable to be T1G
pin or the output of the comparator. This allows the
device to directly time external events using T1G or
analog events using the comparator. See CMCON1
(Register 9-2) for selecting the Timer1 gate source.
This feature can simplify the software for a Delta-Sigma
A/D Converter and many other applications. For more
information on Delta-Sigma A/D Converters, see the
Microchip web site (www.microchip.com).
Timer1 gate can be inverted by using the T1GINV bit
(T1CON<7>), whether it originates from the T1G pin or
the comparator output. This configures Timer1 to
measure either the active high or active low time
between events.
Note:
Timer1 Prescaler
Timer1 Gate
TMR1GE bit (T1CON<6>) must be set to
use either T1G or COUT as the Timer1
gate source. See Register 9-2 for more
information on selecting the Timer1 gate
source.
2003 Microchip Technology Inc.
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