MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 44

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
5.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2T
a small RC delay of 20 ns) and low for at least 2T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.4
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
5.4.1
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
TABLE 5-1:
DS41211A-page 42
Addr
01h
0Bh/
8Bh
81h
85h
Legend:
Note:
TMR0
INTCON
OPTION_REG
TRISIO
Using Timer0 with an External
Clock
Prescaler
Name
module.
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
SWITCHING PRESCALER
ASSIGNMENT
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
REGISTERS ASSOCIATED WITH TIMER0
Timer0 Module Register
GPPU
Bit 7
GIE
—
INTEDG
Bit 6
PEIE
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
T0CS
Bit 5
T0IE
MOVWF 1,
Advance Information
OSC
T0SE
INTE
Bit 4
(and
OSC
GPIE
Bit 3
PSA
Reset, the following instruction sequence (Example 5-
1 and Example 5-2) must be executed when changing
the prescaler assignment from Timer0 to WDT.
EXAMPLE 5-1:
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
BCF
CLRWDT
CLRF
BSF
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
BCF
Bit 2
T0IF
PS2
CLRWDT
BSF
MOVLW
MOVWF
BCF
STATUS,RP0
TMR0
STATUS,RP0
b’00101111’ ;Required if desired
OPTION_REG
b’00101xxx’ ;Set postscaler to
OPTION_REG
STATUS,RP0
INTF
Bit 1
PS1
STATUS,RP0
b’xxxx0xxx’ ;Select TMR0,
OPTION_REG
STATUS,RP0
GPIF
Bit 0
PS0
CHANGING PRESCALER
(TIMER0 WDT)
CHANGING PRESCALER
(WDT TIMER0)
 2003 Microchip Technology Inc.
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
; PS2:PS0 is
; 000 or 001
;
; desired WDT rate
;Bank 0
;Clear WDT and
; prescaler
;Bank 1
; prescale, and
; clock source
;
;Bank 0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
POR, BOD
Value on
Value on
all other
Resets