MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 27

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

FIGURE 3-6:
3.6.4
The IRCF bits can be modified at any time, regardless
of which clock source is currently being used, as the
system clock. The internal oscillator allows users to
change the frequency during RUN time. This is
achieved by modifying the IRCF bits in the OSCCON
register. The sequence of events that occur after the
IRCF bits are modified is dependent upon the initial and
final value of the IRCF bits.
3.6.4.1
If the INTRC (IRCF<2:0> = 000) is running and the
INTOSC (IRCF<2:0>
switch delay is enabled before the HTS bit will be set.
This delay allows the INTOSC to start and stabilize.
The switch will occur on the next falling edge after the
timer expires. If the WDT and Fail-Safe Clock Monitor
are disabled, the INTRC will be disabled to conserve
power and the LTS bit (OSCCON<1>) is cleared.
Time sensitive code should wait for the HTS bit
(OSCCON<2>) to become set before continuing. This
bit can be monitored to ensure that the frequency is
stable before using the system clock in time critical
applications.
3.6.4.2
If the INTOSC (IRCF<2:0>
INTRC (IRCF<2:0> = 000) is requested, the 5 s delay
is enabled before the LTS bit will be set indicating the
INTRC is stable. The switch will occur on the next
falling edge after the timer expires. The delay will not
occur if the Fail-Safe Clock Monitor or WDT are
 2003 Microchip Technology Inc.
OSC2
OSC1
MODIFYING THE IRCF BITS
Switch from 31 kHz up to 125 kHz to
8 MHz
Switch from 125 kHz to 8 MHz down
to 31 kHz
Primary Oscillator
PIC12F683 CLOCK DIAGRAM
000) is selected, a 5 s clock
Oscillator
INTOSC
Internal
Source
8 MHz
31 kHz
Source
INTRC
Sleep
Block
000) is running and
Advance Information
500 kHz
250 kHz
125 kHz
31 kHz
8 MHz
4 MHz
2 MHz
1 MHz
OSCCON<6:4>
enabled for the INTRC will already be active. The
INTOSC is disabled to conserve power and the HTS bit
is cleared.
3.6.4.3
If a different INTOSC frequency is selected, there is no
need for a 5 s delay. The new INTOSC frequency will
already be stable and the switch will occur on the next
falling edge of the new frequency.
3.6.5
The following sequence is performed when the IRCF
bits are changed and the system clock is the internal
oscillator.
1.
2.
3.
4.
111
110
101
100
011
010
001
000
Note:
The IRCF bits are modified.
The clock switching circuitry waits for a falling
edge of the current clock, at which point
CLKOUT is held low.
The clock switching circuitry then waits for the
next falling edge of the requested clock, after
which it switches to this new clock source and
updates the HTS/LTS bit as appropriate.
Oscillator switchover is complete.
LP, XT, HS, RC, EC
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a fre-
quency that may be out of the V
cation range; for example, V
IRCF = 111 (8 MHz).
CLOCK TRANSITION SEQUENCE
Power-up Timer, WDT, Fail-Safe Clock Monitor
Internal Oscillator
Switch within 125 kHz to 8 MHz
FOSC2:FOSC0, SCS
PIC12F683
DS41211A-page 25
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Peripherals
= 2.0V and
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CPU
specifi-