MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 83

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.3.1
PIC12F683 has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the
MCLR pin no longer be tied directly to V
an RC network, as shown in Figure 12-2, is
suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the configuration word. When cleared,
MCLR is internally tied to V
pull-up is enabled for the MCLR pin. In-Circuit Serial
Programming is not affect by selecting the internal
MCLR option.
FIGURE 12-2:
12.3.2
The on-chip POR circuit holds the chip in Reset until
V
operation. To take advantage of the POR, simply tie
the MCLR pin through a resistor to V
eliminate external RC components usually needed to
create Power-on Reset. A maximum rise time for V
is required. See Section 15.0 “Electrical Specifica-
tions” for details. If the BOD is enabled, the maximum
rise time specification does not apply. The BOD
circuitry will keep the device in Reset until V
reaches V
Detect (BOD)”).
 2003 Microchip Technology Inc.
DD
Note:
has reached a high enough level for proper
V DD
R1
1k
C1
0.1 f
(optional, not critical)
The POR circuit does not produce an
internal Reset when V
enable the POR, V
minimum of 100 s.
BOD
MCLR
POWER-ON RESET (POR)
or greater
(see Section 12.3.5 “Brown-Out
RECOMMENDED
CIRCUIT
DD
DD
and an internal weak
must reach Vss for a
MCLR
DD
PIC12F683
declines. To re-
DD
DD
. The use of
MCLR
. This will
Advance Information
DD
DD
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting” (DS00607).
12.3.3
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates from the 31 kHz
INTRC oscillator. For more information on the internal
oscillator block, see Section 3.5 “Internal Oscillator
Block”. The chip is kept in Reset as long as PWRT is
active. The PWRT delay allows additional time for the
V
PWRTE can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Detect is
enabled, although it is not required.
The Power-up Time delay will vary from chip-to-chip
and due to:
• V
• Temperature variation
• Process variation
See DC parameters for details (Section 15.0 “Electri-
cal Specifications”).
12.3.4
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
DD
DD
to rise to an acceptable level. A configuration bit,
variation
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
PIC12F683
DS41211A-page 81