MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 29

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

3.6.7
When SCS bit (OSCCON<0>) is cleared, a clock
transition is generated if the system clock is not already
using the INTOSC. The event will clear the OSTS bit,
switch the system clock from the primary system clock
as determined by FOSC<2:0> in the configuration
word, to the secondary clock, INTOSC, and shut down
the primary system clock to conserve power.
After the SCS bit is changed, the frequency may not be
stable immediately. The appropriate HTS/LTS bit will be
set when the INTOSC/INTRC is stable, after approxi-
mately 1 s. There will not be a delay if the device
switches to the INTRC (31 kHz) and the Fail-Safe
Clock Monitor or WDT is enabled.
FIGURE 3-7:
 2003 Microchip Technology Inc.
SYSTEM_CLOCK
Note 1: T
PROGRAM
COUNTER
PRIMARY TO SECONDARY
OSCILLATOR SWITCH
2: T
3: T
4: T
INTOSC
OSC1
SCS
OSC
SCS
INT
DLY
= 32 s maximum.
= 1 T
= 1 T
= 50 ns minimum.
Q1
PRIMARY (XT, HS, LP, EC, EXTRC) TO SECONDARY OSCILLATOR SWITCH
INT
INT
.
Q2
.
T
PC
OSC
Q3
T
INT
Q4
Advance Information
Q1
T
T
SCS
DLY
Q2
PC + 1
Q3
After a clock switch has been executed, the OSTS bit
is cleared, indicating a Low-power mode, and the
device does not run from the primary system clock. The
internal Q clocks are held in the Q1 state until next
falling edge after the INTOSC is stable. After the delay,
the clock input to the Q clocks is released and
operation resumes (see Figure 3-7).
Q4
Q1
Q2
PC + 2
PIC12F683
Q3
DS41211A-page 27
Q4
PC + 3
Q1