MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 49

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

7.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 7-1.
TMR2 can be shut off by clearing control bit TMR2ON
(T2CON<2>)
Figure 7-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
REGISTER 7-1:
 2003 Microchip Technology Inc.
TIMER2 MODULE
bit 7
bit 6-3
bit 2
bit 1-0
to
minimize
bit 7
Unimplemented: Read as ‘0’
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 =1:1 Postscale
0001 =1:2 Postscale
•
•
•
1111 =1:16 Postscale
TMR2ON: Timer2 On bit
1 =Timer2 is on
0 =Timer2 is off
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
T2CON — TIMER2 CONTROL REGISTER (ADDRESS: 12h)
Legend:
R = Readable bit
- n = Value at POR
U-0
—
power
TOUTPS3
R/W-0
consumption.
Advance Information
TOUTPS2
R/W-0
W = Writable bit
‘1’ = Bit is set
TOUTPS1
R/W-0
7.1
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset. The input clock (F
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
TMR2 is not cleared when T2CON is written.
Watchdog Timer Reset or Brown-out Reset)
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Operation
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
OSC
PIC12F683
/4) has a prescale option
x = Bit is unknown
R/W-0
DS41211A-page 47
R/W-0
bit 0