LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 10

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Table of Contents
List of Tables
Table 1.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 6-1.
Table 7-1.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 10-1.
Table 10-2.
Table 11-1.
Table 12-1.
Table 13-1.
Table 14-1.
Table 14-2.
Table 14-3.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 18-1.
Table 18-2.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 19-5.
Table 19-6.
Table 19-7.
Table 19-8.
Table 19-9.
Table 19-10. Analog Comparator Voltage Reference Characteristics .................................................... 397
Table 19-11.
Table 19-12. Hibernation Module Characteristics ................................................................................. 398
Table 19-13. SSI Characteristics ........................................................................................................ 399
Table 19-14. JTAG Characteristics ..................................................................................................... 400
10
Documentation Conventions ............................................................................................ 17
Memory Map ................................................................................................................... 38
Exception Types .............................................................................................................. 40
Interrupts ........................................................................................................................ 41
JTAG Port Pins Reset State ............................................................................................. 44
JTAG Instruction Register Commands ............................................................................... 49
System Control Register Map ........................................................................................... 59
Hibernation Module Register Map ................................................................................... 115
Flash Protection Policy Combinations ............................................................................. 131
Flash Resident Registers ............................................................................................... 132
Flash Register Map ........................................................................................................ 132
GPIO Pad Configuration Examples ................................................................................. 156
GPIO Interrupt Configuration Example ............................................................................ 156
GPIO Register Map ....................................................................................................... 157
16-Bit Timer With Prescaler Configurations ..................................................................... 197
Timers Register Map ...................................................................................................... 203
Watchdog Timer Register Map ........................................................................................ 230
UART Register Map ....................................................................................................... 258
SSI Register Map .......................................................................................................... 304
Examples of I
Inter-Integrated Circuit (I
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 347
Comparator 0 Operating Modes ..................................................................................... 366
Comparator 1 Operating Modes ...................................................................................... 367
Internal Reference Voltage and ACREFCTL Field Values ................................................. 367
Analog Comparators Register Map ................................................................................. 369
Signals by Pin Number ................................................................................................... 378
Signals by Signal Name ................................................................................................. 382
Signals by Function, Except for GPIO ............................................................................. 386
GPIO Pins and Alternate Functions ................................................................................. 390
Temperature Characteristics ........................................................................................... 392
Thermal Characteristics ................................................................................................. 392
Maximum Ratings .......................................................................................................... 393
Recommended DC Operating Conditions ........................................................................ 393
LDO Regulator Characteristics ....................................................................................... 394
Detailed Power Specifications ........................................................................................ 395
Flash Memory Characteristics ........................................................................................ 396
Phase Locked Loop (PLL) Characteristics ....................................................................... 396
Clock Characteristics ..................................................................................................... 396
Crystal Characteristics ................................................................................................... 397
Analog Comparator Characteristics ................................................................................. 397
I
2
C Characteristics ......................................................................................................... 397
2
C Master Timer Period versus Speed Mode ............................................... 333
2
C) Interface Register Map ......................................................... 342
Preliminary
October 09, 2007