LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 275

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

UART Interrupt Mask (UARTIM)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x038
Type R/W, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:11
10
9
8
7
6
5
RO
RO
31
15
0
0
Register 10: UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
RO
RO
30
14
0
0
reserved
reserved
Name
OEIM
BEIM
PEIM
FEIM
RTIM
TXIM
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
OEIM
R/W
RO
26
10
0
0
Reset
0x00
0
0
0
0
0
0
BEIM
R/W
RO
25
0
9
0
Preliminary
PEIM
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller.
UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller.
UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller.
UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller.
UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller.
UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller.
R/W
RO
24
0
8
0
reserved
FEIM
R/W
RO
23
0
7
0
RTIM
R/W
RO
22
0
6
0
TXIM
R/W
RO
21
0
5
0
RXIM
R/W
RO
20
0
4
0
LM3S1911 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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