LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 398

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Electrical Characteristics
19.2.5
398
a. Values depend on the value programmed into the TPR bit in the I
b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time
c. Specified at a nominal 50 pF load.
Figure 19-2. I
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 V
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 19-12. Hibernation Module Characteristics
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
Parameter No.
Parameter No
programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table
above. The I
period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above
values are minimum values.
I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
H1
H2
H3
H4
H5
H6
H7
I2CSDA
I3
I4
I5
I6
I7
I8
I9
I2CSCL
b
a
c
a
a
a
a
t
t
2
t
Parameter
HIB_REG_WRITE
HIB_TO_VDD
2
t
WAKE_ASSERT
C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low
XOSC_SETTLE
Parameter
t
C Timing
I1
WAKETOHIB
t
t
t
HIB_HIGH
HIB_LOW
t
SCSR
t
t
t
t
t
SRT
SFT
SCS
DH
HT
DS
Parameter Name
I2CSCL/I2CSDA rise time (V
Data hold time
I2CSCL/I2CSDA fall time (V
Clock High time
Data setup time
Start condition setup time (for repeated start condition
only)
Stop condition setup time
Internal 32.768 KHz clock reference rising edge to /HIB asserted
Internal 32.768 KHz clock reference rising edge to /HIB deasserted
/WAKE assertion time
/WAKE assert to /HIB desassert
XOSC settling time
Time for a write to non-volatile registers in HIB module to complete
HIB deassert to VDD and VDD25 at minimum operational level
I2
I4
Preliminary
a
DC
Parameter Name
I6
IH
IL
or powered down with the same regulator controlled
=2.4 V to V
=0.5 V to V
I7
2
C Master Timer Period (I2CMTPR) register; a TPR
IL
IH
=0.5 V)
=2.4 V)
I5
I8
Min
24
18
36
24
2
-
-
Nom
I3
9
-
-
-
-
-
-
(see note b)
Max
10
-
-
-
-
-
Min
62
62
20
92
-
-
-
October 09, 2007
Nom
200
30
system clocks
system clocks
system clocks
system clocks
system clocks
-
-
-
-
-
Max
124
250
Unit
I9
ns
ns
-
-
-
-
-
Unit
ms
μs
μs
μs
μs
μs
μs