LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 66

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LM3S1911-IRN20-A0T

Manufacturer Part Number
LM3S1911-IRN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
System Control
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
66
Reset
Reset
Type
Type
Bit/Field
31:7
5:2
6
1
0
RO
RO
31
15
0
0
Register 5: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
RO
RO
30
14
0
0
reserved
reserved
reserved
PLLLIM
BORIM
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
RO
RO
26
10
0
0
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is promoted to a
controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS
is set; otherwise, an interrupt is not generated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is promoted to a
controller interrupt. If set, an interrupt is generated if BORRIS is set;
otherwise, an interrupt is not generated.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
PLLLIM
R/W
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
RO
RO
18
0
2
0
October 09, 2007
BORIM
R/W
RO
17
0
1
0
reserved
RO
RO
16
0
0
0

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