LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 74

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
74
Reset
Reset
Type
Type
Bit/Field
30:29
28:23
22:14
31
13
12
11
USERCC2
R/W
RO
31
15
0
0
reserved
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
RO
RO
30
14
0
0
reserved
USERCC2
BYPASS2
PWRDN2
SYSDIV2
reserved
reserved
reserved
PWRDN2
Name
R/W
RO
29
13
0
1
reserved
R/W
RO
28
12
0
0
BYPASS2
R/W
R/W
Type
27
11
R/W
R/W
R/W
R/W
0
1
RO
RO
RO
R/W
RO
26
10
1
0
SYSDIV2
Reset
0x0F
0x0
0x0
0
1
0
1
R/W
RO
25
1
9
0
reserved
Preliminary
Description
Use RCC2
When set, overrides the RCC register fields.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down PLL
When set, powers down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bypass PLL
When set, bypasses the PLL for the clock source.
R/W
RO
24
1
8
0
R/W
RO
23
1
7
0
R/W
RO
22
0
6
0
OSCSRC2
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
RO
RO
18
0
2
0
October 09, 2007
reserved
RO
RO
17
0
1
0
RO
RO
16
0
0
0