LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 14

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Table of Contents
Register 32:
General-Purpose Timers ............................................................................................................. 193
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Watchdog Timer ........................................................................................................................... 229
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 252
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
14
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 192
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 205
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 206
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 208
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 210
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 213
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 215
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 216
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 217
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 219
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 220
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 221
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 222
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 223
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 224
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 225
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 226
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 227
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 228
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 232
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 233
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 234
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 235
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 236
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 237
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 238
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 239
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 240
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 241
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 242
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 243
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 244
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 245
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 246
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 247
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 248
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 249
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 250
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 251
UART Data (UARTDR), offset 0x000 ............................................................................... 260
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 262
UART Flag (UARTFR), offset 0x018 ................................................................................ 264
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 266
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 267
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 268
Preliminary
October 09, 2007