LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 52

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

JTAG Interface
5.4.2.3
5.4.2.4
5.4.2.5
5.4.2.6
52
Figure 5-4. BYPASS Register Format
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 52. Each GPIO
pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. These instructions either force data out of the controller, with
the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris
downloadable from www.luminarymicro.com.
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
TDI
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GPIO PB6
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GPIO m
Preliminary
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®
Family Boundary Scan Description Language (BSDL) files,
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RST
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GPIO m+1
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October 09, 2007
GPIO n
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