LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 350

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LM3S1911-IRN20-A0T

Manufacturer Part Number
LM3S1911-IRN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Inter-Integrated Circuit (I
I2C Master Timer Period (I2CMTPR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x00C
Type R/W, reset 0x0000.0001
350
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 4: I
This register specifies the period of the SCL clock.
RO
RO
30
14
0
0
reserved
Name
TPR
RO
RO
29
13
0
0
2
C) Interface
2
RO
RO
28
12
0
0
C Master Timer Period (I2CMTPR), offset 0x00C
reserved
RO
RO
Type
27
11
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0x1
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SCL Clock Period
This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
2
0
4
0
C clock).
TPR
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
1

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