LM3S1911-IRN20-A0T Luminary Micro, Inc., LM3S1911-IRN20-A0T Datasheet - Page 313

• Manufacturer Part Number: LM3S1911-IRN20-A0T
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
RO
RO
31
15
0
0
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
RO
RO
30
14
0
0
reserved
Name
TXIM
RXIM
RTIM
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
SSI Receive FIFO Interrupt Mask
The TFE values are defined as follows:
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
RO
RO
Value
Value
Value
24
0
8
0
reserved
0
1
0
1
0
1
Description
TX FIFO half-full or less condition interrupt is masked.
TX FIFO half-full or less condition interrupt is not masked.
Description
RX FIFO half-full or more condition interrupt is masked.
RX FIFO half-full or more condition interrupt is not masked.
Description
RX FIFO time-out interrupt is masked.
RX FIFO time-out interrupt is not masked.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S1911 Microcontroller
TXIM
R/W
RO
19
0
3
0
RXIM
R/W
RO
18
0
2
0
RTIM
R/W
RO
17
0
1
0
RORIM
R/W
RO
16
0
0
0
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