FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 107

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

PLL CONTROL
interface. The V
on-Reset signal to initialize these components.
Internal PWRGOOD
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as V
and off. When the internal PWRGOOD signal is
“1” (active), V
host interface is active.
PWRGOOD signal is “0” (inactive), V
3.7V, and the FDC37B77x host interface is
inactive; that is, ISA bus reads and writes will
not be decoded.
The FDC37B77x device pins nPME, CLOCKI32,
KCLK, MCLK, IRRX, nRI1, nRI2 and RXD2 are
part of the PME interface and remain active
when the internal PWRGOOD signal has gone
inactive, provided V
PWRGOOD signal is also used to determine the
clock source for the CIrCC CIR and to disable
the IR Half Duplex Timeout.
(CR24.1)
1
0
0
0
0
cc
is > 3.7V, and the FDC37B77x
TR
PME POWER
(CR22.7)
pin generates a V
TR
TABLE 43 - FDC37B77x PLL CONTROLS AND SELECTS
is powered. The internal
X
0
0
1
1
When the internal
PWRGOOD
INTERNAL
cc
TR
cycles on
X
0
1
0
1
cc
Power-
is
107
All PLLs Powered Down
32KHz PLL Unpowered, Not Selected,
14MHz PLL Powered, Selected.
32KHz PLL Powered, Selected,
14MHz PLL Unpowered, Not Selected.
32KHz PLL Powered, Not Selected, 14MHz PLL
Powered, Selected.
Note: If V
wake-up events when V
be at its full minimum potential at least 10 s
before V
and V
difference between the two supplies must not
exceed 500mV.
32.768 kHz TRICKLE CLOCK INPUT
The FDC37B77x utilizes a 32.768 kHz trickle
clock input and a clock multiplier (PLL) to drive
the CIrCC and PME interface when V
removed. The PME Power bit, CR22.7, is used
to enable (power-up) the 32.768 kHz trickle
clock PLL. When the PME Power bit is set to
“1” (active), the 32.768 kHz trickle clock PLL is
running and can replace the 14.318 MHz clock
source for the PME Wake Events, depending
upon the state of the internal PWRGOOD signal
(Table 43). When the PME Power bit is reset to
“0” (inactive/default), the 32.768 kHz trickle
clock PLL is unpowered.
cc
cc
TR
begins a power-on cycle. When V
are fully powered, the potential
is to be used for programmable
DESCRIPTION
CC
is removed, V
cc
has been
TR
must
TR