FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 78

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status
Interrupt
(ELSI)
Interrupt ID
Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 3)
Parity Error
(PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
BIT 2
Table 33 - Register Summary for an Individual UART Channel (continued)
Register (LD8:CRC3[7:0]) and UART2 FIFO Control Shadow Register (LD8:CRC4[7:0]).
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EMSI)
Interrupt ID
Bit (Note 5)
DMA Mode
Select
6)
Parity Enable
(PEN)
OUT2
(Note 3)
Framing Error
(FE)
Delta Data
Carrier Detect
(DDCD)
Bit 3
Bit 3
Bit 11
BIT 3
(Note
Data Bit 4
Data Bit 4
0
0
Reserved
Even Parity
Select (EPS)
Loop
Break
Interrupt (BI)
Clear to Send
(CTS)
Bit 4
Bit 4
Bit 12
BIT 4
78
Data Bit 5
Data Bit 5
0
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data Set
Ready (DSR)
Bit 5
Bit 5
Bit 13
BIT 5
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty
(TEMT)
(Note 2)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
BIT 6
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
0
Error in
RCVR FIFO
(Note 5)
Data Carrier
Detect (DCD)
Bit 7
Bit 15
Bit 7
BIT 7