FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 145

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

Note:
Note:
Note:
Note:
Note:
DMA Channel
Select
Default = 0x04
on Vcc POR or
Reset_Drv
NAME
And by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
nSMI must be disabled to use IRQ2.
IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
All IRQ’s are available in Serial IRQ mode. Only IRQ[3:7] and IRQ[10:12] are available in
Parallel IRQ mode.
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
For the UART 2 logical device, by setting the DMA Enable bit.
specification.
DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER
For the RTC by (refer to the RTC section of this spec).
For the KYBD by (refer to the KYBD controller section of this spec).
Table 58 - DMA Channel Select Configuration Register Description
REG INDEX
0x74 (R/W)
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
145
DEFINITION
Refer to the IrCC
STATE
C