FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 93
FDC37B77X
Manufacturer Part Number
FDC37B77X
Description
ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B77X.pdf
(196 pages)
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Register Definitions
The register definitions are based on the
standard IBM addresses for LPT.
standard printer ports are supported.
additional registers attach to an upper bit
decode of the standard LPT port definition
Note 1: These addresses are added to the parallel port base address as selected by configuration
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
NAME
register or jumpers.
*Refer to ECR Register Description
MODE
000
001
010
011
100
101
110
111
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the configuration registers)
Reserved
Test mode
Configuration mode
ADDRESS (Note 1)
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+401h R/W
+402h R/W
+400h R
Table 37 - ECP Register Definitions
Table 38 - Mode Descriptions
All of the
The
DESCRIPTION*
93
ECP MODES
to avoid conflict with standard ISA devices. The
port is equivalent to a generic parallel port
interface and may be operated in that mode.
The port registers vary depending on the mode
field in the ecr. The table below lists these
dependencies. Operation of the devices in
modes other that those specified is undefined.
000-001
011
010
011
110
111
111
All
All
All
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
FUNCTION
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