FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 90

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
Vocabulary
The following terms are used in this document:
assert: When a signal asserts it transitions to a
forward: Host to Peripheral communication.
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
High performance half-duplex forward and
reverse channel
Interlocked handshake, for fast reliable
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
"true" state, when a signal deasserts it
transitions to a "false" state.
Registers.
Addr/RLE
compress
nBusy
PD7
D7
0
0
intrValue
MODE
nAck
PD6
D6
0
0
Direction
PError
PD5
D5
0
Parallel Port IRQ
Parallel Port Data FIFO
nErrIntrEn
ackIntEn
ECP Data FIFO
Select
PD4
Test FIFO
D4
1
Address or RLE field
90
reverse: Peripheral to Host communication
Pword: A port word; equal in size to the width
1
0
These terms may be considered synonymous:
Reference Document:
Capabilities Port Protocol and ISA Interface
Standard, Rev 1.14, July 14, 1993.
document is available from Microsoft.
The bit map of the Extended Parallel Port
registers is:
SelectIn
dmaEn
nFault
PD3
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
D3
0
of the ISA interface. For this
implementation, PWord is always 8
bits.
A high level.
A low level.
serviceIntr
PD2
nInit
D2
0
0
Parallel Port DMA
autofd
PD1
full
D1
IEEE 1284 Extended
0
0
strobe
empty
PD0
D0
0
0
Note
2
1
1
2
2
2
This