FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 139

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

OSC
Default = 0x04, on
Vcc POR or
Reset_Drv hardware
signal.
Chip Level
Vendor Defined
Configuration
Address Byte 0
Default
=0
=0
on Vcc POR or
Reset_Drv
Configuration
Address Byte 1
Default = 0x03
on Vcc POR or
Reset_Drv
Default = 0x00
on VCC POR and
Hard Reset
Chip Level
Vendor Defined
x
x
F0 (Sysopt=0)
70 (Sysopt=1)
REGISTER
0x29 -0x2A Reserved - Writes are ignored, reads return 0.
ADDRESS
0x24 R/W
0x25
0x26
0x27
0x28
Table 54 - Chip Level Registers
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0
= 1
Bit[7] Reserved
Reserved - Writes are ignored, reads return 0.
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 1
Bit[7:0] Configuration Address Bits [15:8]
See Note 1
Bits[7:0] Reserved - Writes are ignored, reads
return 0.
PLL is on (backward Compatible)
PLL is off
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
12-Bit Address Qualification
16-Bit Address Qualification
139
DESCRIPTION
STATE
C
C
C