FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 75

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
-
-
BAUD RATE
DESIRED
Bit 0=1 as long as there is one byte in the
RCVR FIFO.
Bits 1 to 4 specify which error(s) have
occurred. Character error status is handled
115200
230400
19200
38400
57600
134.5
Table 31 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
50
75
GENERATE 16X CLOCK
DIVISOR USED TO
32770
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
BETWEEN DESIRED AND ACTUAL
75
PERCENT ERROR DIFFERENCE
-
-
-
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
the same way as when in the interrupt
mode, the IIR is not affected since EIR bit
2=0.
Bit 5 indicates when the XMIT FIFO is
empty.
Bit 6 indicates that both the XMIT FIFO and
shift register are empty.
Bit 7 indicates whether there are any errors
in the RCVR FIFO.
0.001
0.004
0.005
0.030
0.16
0.16
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-
1
SPEED BIT
HIGH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
2