FDC37B77X SMSC Corporation, FDC37B77X Datasheet - Page 136

• Manufacturer Part Number: FDC37B77X
• Description: ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
• Manufacturer: SMSC Corporation

Note 1:
Note 2:
Note 3:
Chip Level (Global) Control/Configuration
Registers[0x00-0x2F]
The chip-level (global) registers lie in the
address range [0x00-0x2F]. The design MUST
use all 8 bits of the ADDRESS Port for register
selection. All unimplemented registers and bits
ignore writes and return zero when read.
Config Control
Default = 0x00
on Vcc POR or
Reset_Drv
INDEX
0xF6 :
FB
REGISTER
This register contains some bits that are read or write only.
Bit 0 is not cleared by HARD RESET.
CR22 bit 5 and bit 7 are reset by VTR POR, only.
TYPE
RESET
HARD
ADDRESS
0x02 W
0x00 -
-
0x01
Chip (Global) Control Registers
Table 53 - Chip Level Registers
POR
VCC
-
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
RESET
SOFT
-
136
The INDEX PORT is used to select a
configuration register in the chip.
PORT is then used to access the selected
register. These registers are accessible only in
the Configuration Mode.
DESCRIPTION
POR
VTR
-
Reserved
CONFIGURATION REGISTER
The DATA
STATE
C