mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 10

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Features
3.5
The 64 Kbyte data RAM and the 16 Kbyte cache RAM for the processors are built using a RAM compiler.
Both RAM blocks connect directly to the RAM controller via a standard single-port synchronous SRAM
interface.
3.5.1
The 16-Kbyte cache can be configured into one of three possible organizations: a 16-Kbyte instruction
cache, a 16-Kbyte data cache or a split 8-Kbyte instruction/8-Kbyte data cache. The configuration is
software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all
configurations, the cache is a direct-mapped single-cycle memory.
3.5.2
The SRAM module provides a general-purpose 64-Kbyte memory implemented as four 16-Kbyte blocks
that the ColdFire core can access in a single cycle. The location of the memory block can be set to any
64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses
or memory-referencing commands from the debug module.
The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FECs.
The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer
schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize
system performance. As an example, system performance can be increased significantly if Ethernet
packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
3.6
The MCF5275 family incorporates several low power modes of operation which are entered under
program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit
monitors the input supply and forces an MCU reset as the supply voltage rises.
3.7
The MCF5275 family contains up to two 10/100 BaseT fast Ethernet Controllers (FECs). Refer to
for device configurations.
Each FEC includes these distinctive features:
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IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
Built-in FIFO and DMA controller
Support for different Ethernet physical interfaces:
— 100Mbps IEEE 802.3 MII
— 10Mbps IEEE 802.3 MII
On-chip Memories
Power Management
Fast Ethernet Controller (FEC)
Cache
SRAM
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Preliminary
Freescale Semiconductor
Table 1