mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 26

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
4.8
Table 10
26
Transmit Enable
Transmit Data 0
Collision
Receive Clock
Receive Data Valid
Receive Data 0
Carrier Receive Sense FECn_CRS
Transmit Data 1–3
Transmit Error
Receive Data 1–3
Receive Error
Signal Name
describes QSPI signals.
Queued Serial Peripheral Interface (QSPI)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
FECn_TXEN
FECn_TXD0
FECn_COL
FECn_RXCLK
FECn_RXDV
FECn_RXD0
FECn_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data
FECn_TXER
FECn_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data
FECn_RXER
Abbreviation
Table 9. Ethernet Module (FEC) Signals (continued)
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first FECn_TXCLK following the final nibble of the frame.
FECn_TXD0 is the serial output Ethernet data and is only valid during
the assertion of FECn_TXEN. This signal is used for 10-Mbps
Ethernet data. It is also used for MII mode data in conjunction with
FECn_TXD[3:1].
Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
Provides a timing reference for FECn_RXDV, FECn_RXD[3:0], and
FECn_RXER.
Asserting the receive data valid (FECn_RXDV) input indicates that the
PHY has valid nibbles present on the MII. FECn_RXDV should remain
asserted from the first recovered nibble of the frame through to the last
nibble. Assertion of FECn_RXDV must start no later than the SFD and
exclude any EOF.
FECn_RXD0 is the Ethernet input data transferred from the PHY to
the media-access controller when FECn_RxDV is asserted. This
signal is used for 10-Mbps Ethernet data. This signal is also used for
MII mode Ethernet data in conjunction with FECn_RXD[3:1].
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
and are valid only during assertion of FECn_TXEN in MII mode.
In Ethernet mode, when FECn_TXER is asserted for one or more
clock cycles while FECn_TXEN is also asserted, the PHY sends one
or more illegal symbols. FECn_TXER has no effect at 10 Mbps or
when FECn_TXEN is negated. Applies to MII mode operation.
transferred from the PHY to the Media Access Controller when
FECn_RXDV is asserted in MII mode operation.
In Ethernet mode, FECn_RXER—when asserted with
FECn_RXDV—indicates that the PHY has detected an error in the
current frame. When FECn_RXDV is not asserted FECn_RXER has
no effect. Applies to MII mode operation.
Preliminary
Function
Freescale Semiconductor
I/O
O
O
O
O
O
I
I
I
I
I
I