mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 15

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
3.17 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers which support 58 interrupt sources on the MCF5275. Each interrupt
controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique
interrupt vector, and 51 of the 58 sources of a given controller provide a programmable level [1-7] and
priority within the level.
3.18 Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMA) Module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four channels that allow byte, word, or
longword operand transfers. These transfers can be single or dual address to off-chip devices or dual
address to on-chip devices.
The DMA contains the following features:
3.19 External Interface Module (EIM)
The external interface module on MCF5275 devices handles the transfer of information between the
internal core and memory, peripherals, or other processing elements in the external address space.
Programmable chip select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select is general purpose;
however, any one of the chip selects can be programmed to provide read and write enable signals suitable
for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is
programmable on all chip selects, and further decoding is available for protection from user mode access
or read-only access.
Freescale Semiconductor
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Four fully independent, programmable DMA controller channels/bus modules
Auto-alignment feature for source or destination accesses
Single- and dual-address transfers
Up to four external request pins (DREQ[3:0])
Channel arbitration on transfer boundaries
Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer
Supports continuous-mode and cycle-steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
Provide two clock data transfers
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Preliminary
Features
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