mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 14

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mcf5274l

Manufacturer Part Number
mcf5274l
Description
Mcf5275 Integrated Microprocessor Family Hardware
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Features
Each of the four timer modules has four operating modes:
3.14 Pulse Width Modulation (PWM) Module
The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having
programmable duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog
converter.
The PWM module has six channels with independent control of left and center aligned outputs on each
channel. The MCF5275 family uses four of these channels namely 0, 1, 2 and 3. The emergency shutdown
functionality (channel 5 only) is not used for the MCF5275 family.
Each of the PWM channels has a programmable period and duty cycle as well as a dedicated counter. A
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
Summary of the main features include:
3.15 Software Watchdog Timer (WDT)
The watchdog timer is a 16-bit timer for helping software recover from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software
must periodically restart the countdown.
3.16 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL),
reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
14
Capture mode
Output mode
Reference compare mode
Independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective
period is reached (PWM counter reaches zero) or when the channel is disabled.
Programmable center or left aligned outputs on individual channels
16-bit PWM resolution available by concatenating 8-bit channels
Four clock sources (A, B, SA and SB) provide for a wide range of frequencies.
Programmable Clock Select Logic
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Preliminary
Freescale Semiconductor

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