mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 61

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mcf5274l

Manufacturer Part Number
mcf5274l
Description
Mcf5275 Integrated Microprocessor Family Hardware
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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10.9 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in
Table 52
Freescale Semiconductor
NUM
G1
G2
G3
G4
SD_SRAS,SD_SCAS
SD_CSn,SD_WE,
CLKOUT High to GPIO Output Valid
CLKOUT High to GPIO Output Invalid
GPIO Input Valid to CLKOUT High
CLKOUT High to GPIO Input Invalid
and
SD_DQS[3:2]
SD_DQS[3:2]
Figure
CLKOUT
CLKOUT
D[31:16]
D[31:16]
A[13:0]
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
15.
DD4
Characteristic
ROW
CMD
Figure 14. DDR Read Timing
DD1
Table 52. GPIO Timing
DD5
Preliminary
COL
CL=2
CL=2.5
DQS Read
Symbol
DD2
t
t
Preamble
CHPOV
t
CHPOI
t
PVCH
DD10
CHPI
DQS Read
Preamble
DD3
Preliminary Electrical Characteristics
WD1 WD2 WD3 WD4
Min
1.5
1.5
9
WD1 WD2 WD3 WD4
-
DD9
DQS Read
Postamble
Max
10
DQS Read
Postamble
-
-
-
Unit
ns
ns
ns
ns
61

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