mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 64

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Preliminary Electrical Characteristics
10.11.2MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
Table 55
The transmitter functions correctly up to a
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FECn_TXCLK frequency.
The transmit outputs (FECn_TXD[3:0], FECn_TXEN, FECn_TXER) can be programmed to transition
from either the rising or falling edge of FECn_TXCLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 18
64
Num
M5
M6
M7
M8
lists MII transmit channel timings.
shows MII transmit signal timings listed in
FECn_RXDV
FECn_RXER
FECn_RXD[3:0] (inputs)
FECn_TXER, FECn_TXCLK)
FECn_RXCLK (input)
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER invalid
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER valid
FECn_TXCLK pulse width high
FECn_TXCLK pulse width low
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Figure 17. MII Receive Signal Timing Diagram
Characteristic
Table 55. MII transmit channel timings.
M1
FECn
M2
_TXCLK maximum frequency of 25 MHz +1%. There is
Preliminary
M3
Table
55.
5
—
35%
35%
M4
Min
—
25
65%
65%
Max
ns
ns
FECn_TXCLK
period
FECn_TXCLK
period
Freescale Semiconductor
Unit