mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 25

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

4.6
Table 8
4.7
The following signals are used by the Ethernet modules for data and clock signals.
Freescale Semiconductor
Management Data
Management Data
Clock
Transmit Clock
SDRAM Clock Out
SDRAM Inverted
Clock Out
SDRAM Synchronous
Row Address Strobe
SDRAM Synchronous
Column Address Strobe
SDRAM Write Enable
SDRAM A10
SDRAM Chip Selects
SDRAM Clock Enable
SDRAM Data Strobes
External Interrupts
Signal Name
Signal Name
describes the external interrupt signals.
Signal Name
External Interrupt Signals
Fast Ethernet Controller Signals
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
FECn_MDIO
FECn_MDC
FECn_TXCLK
DDR_CLKOUT This output signal reflects the internal system clock.
DDR_CLKOUT This output signal reflects the inverted internal system clock.
SD_SRAS
SD_SCAS
SD_WE
SD_A10
SD_CS[1:0]
SD_CKE
SD_DQS[3:2]
IRQ[7:1]
Abbreviation
Abbreviation
Abbreviation
Table 9. Ethernet Module (FEC) Signals
Table 7. SDRAM Controller Signals
Table 8. External Interrupt Signals
External interrupt sources.
IRQ[3:2] can also be configured as DMA request signals DREQ[3:2].
IRQ4 can also be configured as DMA request signals DREQ2.
SDRAM synchronous row address strobe.
SDRAM synchronous column address strobe.
SDRAM write enable.
SDRAM address bit 10 or command.
SDRAM chip select signals.
SDRAM clock enable.
SDRAM byte-lane read/write data strobe signals.
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FECn_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
In Ethernet mode, FECn_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FECn_MDIO
signal. Applies to MII mode operation.
Input clock which provides a timing reference for FECn_TXEN,
FECn_TXD[3:0] and FECn_TXER
Preliminary
Function
Function
Function
Signal Descriptions
I/O
I/O
I
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
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