mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 16

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Features
The key features of the EIM are summarized below:
3.20 Double Data Rate (DDR) Synchronous DRAM
The SDRAMC provides a 16-bit glueless external interface to double-data-rate (DDR) SDRAM memory
devices. It is responsible for providing address, data and control signals for up to two independent
chip-selects.
The SDRAMC includes the following features:
3.21 Resets
The Reset Controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and then to keep a history of what caused the reset.
The MCF5275 family has six (6) sources of reset:
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Eight independent, user-programmable chip-select signals (CS[7:0]) that interface with various
memory types and peripherals
Address masking for 64 Kbyte to 4 gigabyte memory block sizes
Programmable wait states and port sizes
External master access to chip selects
Supports a glueless interface to DDR SDRAMs
16-bit fixed memory port width
32-bit data bus interface to Coldfire core
16 bytes (8 beat x 16-bit) critical word first burst transfer
Up to 14 row address lines, up to 12 column address lines, maximum of two chip selects. The
maximum row bits plus column bits is 24.
Supported SDRAM devices include: 8, 16, 32, 64, and 128Mbyte per chip select
Minimum memory configuration of 8 Mbyte—12 bit row address (RA), 8 bit column address
(CA), 2 bit bank address (BA) and one chip select
Supports page mode to maximize the data rate
Supports sleep mode and self-refresh mode
Error detect and parity check are not supported
External
Power On Reset (POR)
Watchdog timer
PLL Loss of Lock
PLL Loss of Clock
Software
(SDRAM) Controller
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Preliminary
Freescale Semiconductor