mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 30

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
4.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM
logic.
30
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
Breakpoint
Development Serial
Input
Development Serial
Output
Debug Data
Processor Status
Outputs
PWM Output Channel 0 PWM0
PWM Output Channel 1 PWM1
PWM Output Channel 2 PWM2
PWM Output Channel 3 PWM3
Signal Name
Signal Name
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
TRST
TCLK
TMS
TDI
TDO
DSCLK
BKPT
DSI
DSO
DDATA[3:0]
PST[3:0]
Abbreviation
Abbreviation
Table 16. Debug Support Signals
Pulse width modulated output for PWM channel 0.
Pulse width modulated output for PWM channel 1.
Pulse width modulated output for PWM channel 2.
Pulse width modulated output for PWM channel 3.
This active-low signal is used to initialize the JTAG logic
asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Clocks the serial communication port to the BDM module during
packet transfers.
Used to request a manual breakpoint.
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
This internally-registered signal provides serial output communication
for BDM module responses.
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Indicate core status, as shown in
synchronous with the processor clock; status is unrelated to the
current bus transfer. The CLKOUT signal can be used by the
development system to know when to sample PST[3:0].
Table 15. PWM Signals
Preliminary
Function
Function
Table
17. Debug mode timing is
Freescale Semiconductor
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I