z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 131

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
PWM Duty Cycle Registers
Independent and Complementary PWM Outputs
EDGE-ALIGNED Mode
In EDGE-ALINGED PWM mode, a 12-bit up counter creates the PWM period with a
minimum resolution equal to the PWM clock source period. The counter counts up to the
Reload value, resets to
CENTER-ALINGED Mode
In CENTER-ALINGED PWM mode, a 12-bit up/down counter creates the PWM period
with a minimum resolution equal to twice the PWM clock source period. The counter
counts up to the Reload value and then counts down to 0.
The PWM duty cycle registers (PWMH0D, PWML0D, PWMH1D, PWML1D, PWMH2D,
PWML2D) contain a 16-bit signed value where bit 15 is the sign bit. The duty cycle value is
compared to the current 12-bit unsigned PWM count value. If the PWM duty cycle value is
set less than or equal to 0, the PWM output is deasserted for full PWM period. If the PWM
duty cycle value is set to a value greater than the PWM Reload value, the PWM output is
asserted for full PWM period.
The six PWM outputs are configured to operate independently or as three complementary
pairs. Operation as six independent PWM channels are enabled by setting the INDEN bit
in the
output uses its own PWM duty cycle value.
When PWM outputs are configured to operate as three complementary pairs, the PWM
duty cycle values PWMH0D, PWMH1D, and PWMH2D control the modulator output. In
COMPLEMENTARY OUTPUT mode deadband time is also inserted.
The POLx bits in the
the high- and low-side signals. As illustrated in
when the POLx bits are cleared to 0, the PWM high-side output will start in the on-state
and transits to the off-state when the PWM timer count reaches the programmed duty
cycle. The low-side PWM value starts in the off-state and transits to the on-state as the
PWM timer count reaches the value in the associated duty cycle register. Alternately,
setting the POLx causes the high-side output to start in the off-state and the low-side
output to start in the on-state.
Center-Aligned PWM Mode Period
Edge-Aligned PWM Mode Period
PWM Control 1 Register
PWM Control 1 Register (PWMCTL1)
000H
P R E L I M I N A R Y
, and then resumes counting.
(PWMCTL1). In INDEPENDENT mode, each PWM
=
=
Prescaler Reload Value
------------------------------------------------------------ -
2 Prescaler
--------------------------------------------------------------------- -
×
Figure 21
f
PWMclk
×
f
PWMclk
and
×
Reload Value
select the relative polarity of
Figure 22
Multi-Channel PWM Timer
Product Specification
ZNEO
on page 116,
™
Z16F Series
117