z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 232

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
1. Software configures the controller for operation as a Slave in 7-bit addressing mode as
2. The Master initiates a transfer, sending the address byte. The SLAVE mode I
3. Software responds to the interrupt by reading the I2CISTAT register, clearing the
4. SCL is released and the first data byte is shifted out.
5. When the first bit of the first data byte is transferred, the I
6. Software responds to the transmit data interrupt (
7. When the Master receives the data byte, the Master transmits an Acknowledge
8. The bus cycles through steps 5–7 until the last byte has been transferred. If software
9. Software responds to the Not Acknowledge interrupt by clearing the
10. When the Master completes the last acknowledge cycle, it asserts the STOP or
11. The Slave I
– Initialize the MODE field in the I
– Optionally set the
– Initialize the
– Set
– Program the Baud Rate High and Low Byte registers for the I
follows.
Controller finds an address match and detects the R/W bit = 1 (read by Master from
Slave). The I
transaction.The
RD
bit. When
register. Software sets the
When the Master initiates the data transfer, the I
software has written the first data byte to the I2CDATA register.
bit, which asserts the transmit data interrupt.
byte into the I2CDATA register, which clears
instruction (or Not Acknowledge instruction for the last data byte).
has not yet loaded the next data byte when the Master brings SCL Low to transfer the
most significant data bit, the Slave I
register is written.
When the Slave receives a Not Acknowledge instruction, the I
NCKI
I2CCTL register and by asserting the
data register.
RESTART condition on the bus.
I2CISTAT register).
or MASTER/SLAVE mode with 7-bit addressing.
bit is set = 1, indicating a read from the Slave.
IEN
bit in the I2CISTAT register and generates the Not Acknowledge interrupt.
RD
= 1 in the I
2
C Controller asserts the STOP/RESTART interrupt (set
2
= 1, software responds by loading the first data byte into the I2CDATA
C Controller acknowledges, indicating that it is ready to accept the
SLA
SAM
[6:0] bits in the I2C Slave Address register.
GCE
bit in the I2CISTAT register is set = 1, causing an interrupt. The
2
P R E L I M I N A R Y
C Control register. Set
bit.
TXI
bit in the I2CCTL register to enable transmit interrupts.
2
2
C Mode register for either SLAVE-ONLY mode
C Controller holds SCL Low until the data
FLUSH
bit of the I2CCTL register to empty the
NAK
TDRE
2
C Controller holds SCL Low until
TDRE
= 0 in the I
.
= 1) by loading the next data
2
I2C Master/Slave Controller
C controller sets the
Product Specification
2
ZNEO
2
C Control register.
C Controller sets the
2
C baud rate.
SPRS
TXI
™
Z16F Series
bit in the
bit in
2
C
TDRE
SAM
218