z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 198

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

™
ZNEO
Z16F Series
Product Specification
184
Multi-Master SPI Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must be configured in open-
drain mode to prevent bus contention. At any time, only one SPI device is configured as
the master and all other devices on the bus are configured as slaves. The master asserts the
SS pin on the selected slave. Then, the active master drives the clock and transmit data on
the SCK and MOSI pins to the SCK and MOSI pins on the slave (including those slaves
which are not enabled). The enabled slave drives data out its MISO pin to the MISO
master pin.
When the ESPI is configured as a master in a multi-master SPI system, the SS pin must be
configured as an input. The SS input signal on a device configured as a master must
remain High. If the SS signal on the active master goes Low (indicating another master is
accessing this device as a slave), a collision error flag is set in the ESPI status register. The
slave select outputs on a master in a multi-master system must come from GPIO pins.
SPI Slave Operation
The ESPI block is configured for SLAVE mode operation by setting the MMEN bit = 0 in
the ESPICTL register and setting the
bit
in the ESPIMODE register. The SSMD
SSIO
= 0
field of the ESPI mode register is set to 00 for SPI protocol mode. The
,
and
Phase
Clkpol
bits in the ESPICTL register and the NUMBITS field in the ESPIMODE register must
WOR
be set to be consistent with the other SPI devices. Typically for an SPI slave SSPO = 0.
If the slave has data to send to the master, the data must be written to the data register
before the transaction starts (first edge of SCK when SS is asserted). If the data register is
not written prior to the slave transaction, the MISO pin outputs all 1s.
Due to the delay resulting from synchronization of the SS and SCK input signals to the
internal system clock, the maximum SCK baud rate which is supported in SLAVE mode is
the system clock frequency divided by 8. This rate is controlled by the SPI master.
Figure 41
on page 185 illustrates the ESPI configuration in SPI SLAVE mode.
PS022006-0207
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface