z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 186
z16f2811
Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z16F2811.pdf
(383 pages)
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Enhanced Serial Peripheral Interface
Architecture
PS022006-0207
The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface)
and Inter IC Sound (I
The features of the ESPI include:
•
•
•
•
•
•
•
The ESPI is a full-duplex, synchronous, character-oriented channel that supporting a
four-wire interface (serial clock, transmit and receive data, and Slave select). The ESPI
block consists of a shift register, transmit and receive data buffer registers, a baud rate
(clock) generator, control/status registers, and a control state machine. Transmit and
receive transfers are in sync as there is a single shift register for both transmit and receive
data.
Full-duplex, synchronous, character-oriented communication.
Four-wire interface (SS, SCK, MOSI, MISO).
Transmit and receive buffer registers to enable high throughput.
Transfer rates up to maximum of one-fourth the system clock frequency. This is in
SLAVE mode.
Error detection.
Dedicated programmable baud rate generator (BRG).
Data transfer control through polling, interrupt, or DMA.
Figure 34
on page 173 illustrates a block diagram of the ESPI.
2
S) modes of operation.
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
™
Z16F Series
172
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