z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 157

• Manufacturer Part Number: z16f2811
• Description: High Performance Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS022006-0207
In LIN mode, the interrupts defined for normal UART operation still apply with the
following changes:
•
•
•
•
LIN System Clock Requirements
The LIN master provides the timing reference for the LIN network and is required to have a
clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a slave does not
contain autobaud capability, it must include a baud clock which deviates from the masters
by no more than ±1.5%. These accuracy requirements must include effects such as voltage
and temperature drift during operation.
Before sending or receiving messages, the baud reload High/Low registers must be
initialized. Unlike standard UART modes, the baud reload High/Low registers must be
loaded with the baud interval rather than 1/16 of the baud interval.
In order to autobaud with the required accuracy, the LIN slave system clock must be at least
100 times the baud rate.
LIN Mode Initialization and Operation
The LIN protocol mode is selected by setting either the LIN master (
(
register. To access the LIN control register, the mode select (MSEL) field of the LIN-
UART mode select/status register must be
initialized with TEN = 1, REN = 1, all other bits = 0.
LSLV
The break detect interrupt (
The break detect interrupt (
In LIN SLAVE mode, if the BRG counter overflows while measuring the autobaud
Parity error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE)
detected by the slave (break condition for at least 11 bit times). Software uses this
interrupt to start a timer checking for message frame time-out. The duration of the break
is read in the
message has been received if the LIN-UART is in LINSLEEP state.
period (
indicated (
back to
signal. The baud reload high and low registers are not updated by hardware if this
autobaud error occurs. The
bit. The PLE bit indicates that receive data does not match transmit data when the LIN-
UART is transmitting. This applies to both MASTER and SLAVE OPERATING
modes.
), and optionally (for LIN slave) the autobaud enable (
Start
10b
OE
, where the slave ignores the current message and waits for the next Break
RxBreakLength[3:0]
bit in the Status0 register). In this case, software sets the LinState field
bit to beginning of bit 7 of autobaud character) an overrun error is
P R E L I M I N A R Y
BRKD
BRKD
OE
bit is also set if a data overrun error occurs.
bit in status0 register) indicates when a Break is
bit in Status0 register) indicates when a wake-up
010b
field of the Mode Status register.
. The LIN-UART control0 register must be
ABEN
Product Specification
) bits in the LIN control
ZNEO
LMST
™
) or LIN slave
Z16F Series
LIN-UART
143