z16f2811 ZiLOG Semiconductor, z16f2811 Datasheet - Page 57
z16f2811
Manufacturer Part Number
z16f2811
Description
High Performance Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z16F2811.pdf
(383 pages)
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PS022006-0207
DATA[15:0]
ISA-Compatible Mode
ADDR[23:0]
(output)
controlled by the CSxWAIT[3:0] field and the PRxWAIT[1:0] field as shown in the
Select Control Registers
number of system clock cycles. A maximum of 31 Waits states are inserted. An example
of Wait state operation is illustrated in
has been configured to provide two Wait states. See the detailed timing diagrams in
External Interface Timing
Figure 10. External Interface Wait State Operation Example (Write Operation)
Configuring the external interface for ISA mode adjusts the Read timing to follow the ISA
mode commonly employed in PC and related applications. In ISA mode, assertion of the
Read signal (RD) is delayed one-half system clock. Also, an extra Wait state is added
during Read operations.
XIN
WR
CS
TCLK
on page 44. The Wait states idle the ZNEO CPU for the specified
on page 48.
P R E L I M I N A R Y
TWAIT
Figure
State Generator
Enabled in Wait
2 Wait States
10. In this example, the external interface
TWAIT
Product Specification
ZNEO
External Interface
™
Z16F Series
Chip
43
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