peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 174

• Manufacturer Part Number: peb2255
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the
CPU.
This process is repeated until the CPU indicates the end of message by XME command,
after which frame transmission is finished correctly by appending the CRC and closing
flag sequence. Consecutive frames may be share a flag, or may be transmitted as back-
to-back frames, if service of XFIFO is fast enough.
In case no more data is available in the XFIFO prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
by interrupt ISR1.XDU. The frame may be aborted by software using CMDR.SRES.
The data transmission sequence from the CPU’s point of view is outlined in
Figure 58
The activities at both serial and CPU interface during frame transmission (supposed
frame length = 70 bytes) shown in
Data Sheet
Interrupt Driven Data Transmission (flow diagram)
Command
XTF/XHF
N
N
Figure
Command
XTF/XHF
Write Data
(up to 32
to XFIFO
174
59.
Transmit
Pool Ready
End of
Message
START
END
?
?
Signaling Controller Operating Modes
Y
Y
+ XME
bytes)
XPR Interrupt,
XFW Bit in SIS Register
FALC-LH V1.3
or
ITD08565
PEB 2255
Figure
= 1
2000-07
58.