peb2255 Infineon Technologies Corporation, peb2255 Datasheet - Page 49

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peb2255

Manufacturer Part Number
peb2255
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet

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3.3.1.2
In transmit and receive direction of the signaling controller 64-byte deep FIFOs are
provided for the intermediate storage of data between the system internal highway and
the CPU interface. The FIFOs are divided into two halves of 32-bytes. Only one half is
accessible to the CPU at any time.
In case 16-bit data bus width is selected by fixing pin DBW to logical ‘1’ word access to
the FIFOs is enabled. Data output to bus lines D0-D15 as a function of the selected
interface mode is shown in
allowed. The effective length of the accessible part of RFIFO can be changed from
32 bytes (RESET value) down to 2 bytes by programming CCR1.RFT1...0.
Figure 7
Data Sheet
D15
32
32
1
4
3
2
1
FIFO Structure
FIFO Word Access (Intel Mode)
D8 D7
RFIFO
Byte 4
Byte 3
Byte 2
Byte 1
Figure 7
D0
and
49
Figure
D15
8. Of course, byte access is also
Functional Description E1/T1/J1
32
32
1
4
3
2
1
D8
XFIFO
Byte 4
Byte 3
Byte 2
Byte 1
D7
FALC-LH V1.3
PEB 2255
ITD01798
2000-07
D0

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